Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks

Spiking Neural Networks (SNNs) compute in an event-based matter to achieve a more efficient computation than standard Networks. In SNNs, neuronal outputs (i.e. activations) are not encoded with real-valued activations but sequences of binary spikes. The motivation using SNNs over conventional neural networks is rooted the special computational aspects especially very high degree sparsity output activations. Well established architectures for Convolutional (CNNs) feature large spatial arrays Processing Elements (PEs) that remain highly underutilized face activation sparsity. We propose novel architecture optimized processing (CSNNs) our architecture, main strategy use less utilized PEs. PE array used perform convolution only as kernel size, allowing all PEs be active long there spikes process. This constant flow ensured by compressing maps into queues can then processed spike spike. compression performed run-time dedicated circuitry, leading self-timed scheduling. allows time scale directly number A memory organization scheme called interlacing efficiently store and retrieve membrane potentials individual neurons multiple small parallel on-chip RAMs. Each RAM hardwired its PE, reducing switching circuitry RAMs located close proximity respective PE. implemented proposed on FPGA achieved significant speedup compared other implementations while needing hardware resources maintaining lower energy consumption.